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SC16C752
Dual UART with 64-byte FIFO
Rev. 04 -- 20 June 2003 Product data
1. Description
The SC16C752 is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbits/s (3.3 V and 5 V). The SC16C752 offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The SC16C752 is available in a plastic LQFP48 package.
2. Features
s Pin compatible with SC16C2550 with additional enhancements s Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is 3 Mbits/s) s 64-byte transmit FIFO s 64-byte receive FIFO with error flags s Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation s Software/hardware flow control x Programmable Xon/Xoff characters x Programmable auto-RTS and auto-CTS s Optional data flow resume by Xon any character s DMA signalling capability for both received and transmitted data s Supports 5 V, 3.3 V and 2.5 V operation s Software selectable baud rate generator s Prescaler provides additional divide-by-4 function
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
s Fast databus access time s Programmable sleep mode s Programmable serial interface characteristics x 5, 6, 7, or 8-bit characters x Even, odd, or no parity bit generation and detection x 1, 1.5, or 2 stop bit generation s False start bit detection s Complete status reporting capabilities in both normal and sleep mode s Line break generation and detection s Internal test and loop-back capabilities s Fully prioritized interrupt system controls s Modem control functions (CTS, RTS, DSR, DTR, RI, and CD).
3. Ordering information
Table 1: Ordering information Package Name SC16C752IB48 LQFP48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 Type number
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SC16C752
Dual UART with 64-byte FIFO
4. Block diagram
SC16C752
TRANSMIT FIFO REGISTER D0-D7 IOR IOW RESET DATA BUS AND CONTROL LOGIC
TRANSMIT SHIFT REGISTER
TXA, TXB
INTERCONNECT BUS LINES AND CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA, RXB
A0-A2 CSA CSB
REGISTER SELECT LOGIC
DTRA, DTRB RTSA, RTSB OPA, OPB
MODEM CONTROL LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR
CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB
002aaa225
XTAL1 XTAL2
Fig 1. Block diagram.
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SC16C752
Dual UART with 64-byte FIFO
5. Pinning information
5.1 Pinning
43 TXRDYA
39 DSRA
38 CTSA
42 VCC
40 CDA
41 RIA
D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB
1 2 3 4 5 6
37 NC
48 D4
47 D3
46 D2
45 D1
44 D0
36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OPA 31 RXRDYA
SC16C752IB48
7 8 9 30 INTA 29 INTB 28 A0 27 A1 26 A2 25 NC
CSA 10 CSB 11 NC 12
XTAL1 13
XTAL2 14
IOW 15
CDB 16
GND 17
RXRDYB 18
IOR 19
DSRB 20
RIB 21
RTSB 22
CTSB 23
NC 24
002aaa224
Fig 2. Pin configuration.
5.2 Pin description
Table 2: Symbol A0 A1 A2 CDA, CDB Pin description Pin 28 27 26 40, 16 Type I I I I Description Address 0 select bit. Internal registers address selection. Address 1 select bit. Internal registers address selection. Address 2 select bit. Internal registers address selection. Carrier Detect (Active-LOW). These inputs are associated with individual UART channels A and B. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Chip Select (Active-LOW). These pins enable data transfers between the user CPU and the SC16C752 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic LOW on the respective CSA and CSB pins.
CSA, CSB
10, 11
I
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SC16C752
Dual UART with 64-byte FIFO
Table 2: Symbol
Pin description...continued Pin 38, 23 Type I Description Clear to Send (Active-LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the modem or data set is ready to accept transmit data from the SC16C752. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data Set Ready (Active-LOW). These inputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). Data Terminal Ready (Active-LOW). These outputs are associated with individual UART channels A and B. A logic 0 (LOW) on these pins indicates that the SC16C752 is powered-on and ready. These pins can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Signal and power ground. Interrupt A and B (Active-HIGH). These pins provide individual channel interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space, or when a modem status flag is detected. INTA, INTB are in the high-impedance state after reset. Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on IOR will load the contents of an internal register defined by address bits A0-A2 onto the SC16C752 data bus (D0-D7) for access by external CPU. Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on IOW will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2 and CSA and CSB. Not connected. User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of MCR[3]. INTA-INTB are set to active mode and OPA-OPB to a logic 0 when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-State mode and OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset. Reset. This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. RESET is an active-HIGH input. Ring Indicator (Active-LOW). These inputs are associated with individual UART channels, A and B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).
CTSA, CTSB
D0-D4, D5-D7 DSRA, DSRB
44-48, 1-3 39, 20
I/O
I
DTRA, DTRB
34, 35
O
GND INTA, INTB
17 30, 29
I O
IOR
19
I
IOW
15
I
NC OPA, OPB
12, 24, 25, 37 32, 9
O
RESET
36
I
RIA, RIB
41, 21
I
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SC16C752
Dual UART with 64-byte FIFO
Table 2: Symbol
Pin description...continued Pin 33, 22 Type O Description Request to Send (Active-LOW). These outputs are associated with individual UART channels, A and B. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins only affect the transmit and receive operations when Auto-RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the SC16C752. During the local loop-back mode, these RX input pins are disabled and TX data is connected to the UART RX input internally. Receive Ready (Active-LOW). RXRDYA or RXRDYB goes LOW when the trigger level has been reached or the FIFO has at least one character. It goes HIGH when the RX FIFO is empty. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C752. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready (Active-LOW). TXRDYA or TXRDYB go LOW when there are at least a trigger level number of spaces available or when the FIFO is empty. It goes HIGH when the FIFO is full or not empty. Power supply input. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 12). Alternatively, an external clock can be connected to this pin to provide custom data rates. Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output.
RTSA, RTSB
RXA, RXB
5, 4
I
RXRDYA, RXRDYB TXA, TXB
31, 18
O
7, 8
O
TXRDYA, TXRDYB VCC XTAL1
43, 6
O
42 13
I I
XTAL2
14
O
6. Functional description
The SC16C752 UART is pin-compatible with the SC16C2550 UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC16C752 UART can be read at any time during functional operation by the processor. The SC16C752 can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.
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SC16C752
Dual UART with 64-byte FIFO
The SC16C752 has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 - 1).
6.1 Trigger levels
The SC16C752 provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR.
6.2 Hardware flow control
Hardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With Auto-CTS, CTS must be active before the UART can transmit data. Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the levels at which RTS is activated/deactivated. If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
UART 1
UART 2
SERIAL-TOPARALLEL RX FIFO FLOW CONTROL D7-D0
RX
TX
PARALLELTO-SERIAL TX FIFO
RTS
CTS
FLOW CONTROL D7-D0
PARALLELTO-SERIAL TX FIFO FLOW CONTROL
TX
RX
SERIAL-TOPARALLEL RX FIFO
CTS
RTS
FLOW CONTROL
002aaa228
Fig 3. Autoflow control (Auto-RTS and Auto-CTS) example.
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SC16C752
Dual UART with 64-byte FIFO
6.2.1
Auto-RTS Auto-RTS data flow control originates in the receiver block (see Figure 1 "Block diagram." on page 3). Figure 4 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.
RX
START
BYTE N
STOP
START
BYTE N + 1
STOP
START
RTS
IOR
1
2
N
N+1
002aaa226
(1) N = receiver FIFO trigger level. (2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.
Fig 4. RTS functional timing.
6.2.2
Auto-CTS The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.
TX
START
BYTE 0-7
STOP
START
BYTE 0-7
STOP
CTS
002aaa227
(1) When CTS is LOW, the transmitter keeps sending serial data out. (2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but is does not send the next byte. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 5. CTS functional timing.
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SC16C752
Dual UART with 64-byte FIFO
6.3 Software flow control
Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options.
Table 3: EFR[3] 0 1 0 1 X X X 1 0 1 0 0 1 1 X X X 0 1 1 Software flow control options (EFR[0:3]) EFR[2] EFR[1] X X X X 0 1 0 1 1 1 EFR[0] X X X X 0 0 1 1 1 1 TX, RX software flow controls no transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 no receive flow control receiver compared Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Remark: When using software flow control, the Xon/Xoff characters cannot be used for data characters. There are two other enhanced features relating to software flow control:
* Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.
* Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 RX When software flow control operation is enabled, the SC16C752 will compare incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH. To resume transmission, an Xon1,2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears.
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Dual UART with 64-byte FIFO
6.3.2
TX Xoff1/2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0]. Xon1/2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 6 shows an example of software flow control.
6.3.3
Software flow control example
UART1
UART2
TRANSMIT FIFO
RECEIVE FIFO
PARALLEL-TO-SERIAL
DATA
SERIAL-TO-PARALLEL
Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL
Xon-1 WORD
Xon-1 WORD
Xon-2 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-1 WORD
Xoff-2 WORD
COMPARE PROGRAMMED Xon-Xoff CHARACTERS
Xoff-2 WORD
002aaa229
Fig 6. Software flow control example.
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52. UART 1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RCV FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of
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SC16C752
Dual UART with 64-byte FIFO
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0D to UART1, informing UART1 to resume transmission.
6.4 Reset
Table 4 summarizes the state of register after reset.
Table 4: Register Interrupt enable register Interrupt identification register FIFO control register Line control register Modem control register Line status register Modem status register Enhanced feature register Receiver holding register Transmitter holding register Transmission control register Trigger level register
[1]
Register reset functions Reset control RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Reset state All bits cleared. Bit 0 is set. All other bits cleared. All bits cleared. Reset to 00011101 (1D hex). All bits cleared. Bits 5 and 6 set. All other bits cleared. Bits 0-3 cleared. Bits 4-7 input signals. All bits cleared. Pointer logic cleared. Pointer logic cleared. All bits cleared. All bits cleared.
Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET, i.e., they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 5: Signal TX RTS DTR RXRDY TXRDY Signal RESET functions Reset control RESET RESET RESET RESET RESET Reset state high high high high low
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Dual UART with 64-byte FIFO
6.5 Interrupts
The SC16C752 has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5;0]. Table 6 summarizes the interrupt control functions.
Table 6: IIR[5:0] 000001 000110 Interrupt control functions Priority level None 1 Interrupt type none receiver line status Interrupt source none OE, FE, PE, or BI errors occur in characters in the RX FIFO Interrupt reset method none FE, PE, BI: all erroneous characters are read from the RX FIFO. OE: read LSR 001100 000100 2 2 RX time-out RHR interrupt stale data in RX FIFO DRDY (data ready) (FIFO disable) RX FIFO above trigger level (FIFO enable) 000010 3 THR interrupt TFE (THR empty) (FIFO disable) TX FIFO passes above trigger level (FIFO enable) 000000 010000 100000 4 5 6 modem status Xoff interrupt CTS, RTS MSR[3:0] = 0 receive Xoff character(s)/special character read MSR receive Xon character(s)/Read of IIR read IIR or a write to the THR read RHR read RHR
RTS pin or CTS pin change state from read IIR active (LOW) to inactive (HIGH)
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros. For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the LSR.
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6.5.1
Interrupt mode operation In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see if any interrupt needs to be serviced. Figure 7 shows interrupt mode operation.
IOW / IOR INT PROCESSOR
IIR
IER 1 1 1 1
THR
RHR
002aaa230
Fig 7. Interrupt mode operation.
6.5.2
Polled mode operation In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the line status register (LSR). This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 8 shows FIFO polled mode operation.
IOW / IOR PROCESSOR
LSR
IER 0 0 0 0
THR
RHR
002aaa231
Fig 8. FIFO polled mode operation.
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6.6 DMA operation
There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. 6.6.1 Single DMA transfers (DMA mode 0/FIFO disable) Figure 9 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
TX
RX
TXRDY
RXRDY
wrptr
AT LEAST ONE LOCATION FILLED
rdptr
AT LEAST ONE LOCATION FILLED
TXRDY
RXRDY
wrptr
FIFO EMPTY
rdptr
FIFO EMPTY
002aaa232
Fig 9. TXRDY and RXRDY in DMA mode 0/FIFO disable.
Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has been loaded into it. Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty.
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Dual UART with 64-byte FIFO
6.6.2
Block DMA transfers (DMA mode 1) Figure 10 shows TXRDY and RXRDY in DMA mode 1.
wrptr
TX TRIGGER LEVEL TXRDY rdptr
RX
RXRDY
FIFO FULL
AT LEAST ONE LOCATION FILLED
TRIGGER LEVEL wrptr TXRDY RXRDY
rdptr
FIFO EMPTY
002aaa234
Fig 10. TXRDY and RXRDY in DMA mode 1.
Transmitter: TXRDY is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. Receiver: RXRDY becomes active when the trigger level has been reached, or when a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7].
6.7 Sleep mode
Sleep mode is an enhanced feature of the SC16C752 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
* The serial data input line, RX, is idle (see Section 6.8 "Break and time-out
conditions").
* The TX FIFO and TX shift register are empty. * There are no interrupts pending except THR and time-out interrupts.
Remark: Sleep mode will not be entered if there is data in the RX FIFO. In sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO. Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done during sleep mode. Therefore, it is advisable to disable sleep mode using IER[4] before writing to DLL or DLH.
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6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C752 UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 11. The output frequency of the baud rate generator is 16x the baud rate. The formula for the divisor is: XTAL1 crystal input frequency --------------------------------------------------------------------------- prescaler divisor = -------------------------------------------------------------------------------( desired baud rate x 16 ) Where: prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected) prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected). Remark: The default value of prescaler after reset is divide-by-1. Figure 11 shows the internal prescaler and baud rate generator circuitry.
PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 INTERNAL OSCILLATOR LOGIC
MCR[7] = 0 INTERNAL BAUD RATE CLOCK FOR TRANSMITTER AND RECEIVER
INPUT CLOCK REFERENCE CLOCK MCR[7] = 1
XTAL2
BAUD RATE GENERATOR LOGIC
PRESCALER LOGIC (DIVIDE-BY-4)
002aaa233
Fig 11. Prescaler and baud rate generator block diagram.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as no baud clock will be generated. Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz, respectively. Figure 12 shows the crystal clock circuit reference.
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Baud rates using a 1.8432 MHz crystal Divisor used to generate 16 x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Baud rates using a 3.072 MHz crystal Divisor used to generate 16 x clock 2304 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Percent error difference between desired and actual 2.86 0.69 0.026 0.058 Percent error difference between desired and actual
Table 7:
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 8:
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400
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XTAL1
XTAL2
XTAL1
XTAL2 X1 1.8432 MHz 1.5 k C1 22 pF C2 47 pF
002aaa169
X1 1.8432 MHz C1 47 pF C2 100 pF
Fig 12. Crystal oscillator connections.
7. Register descriptions
Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 9.
Table 9: A2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1
[1] [2] [3] [4] [5] [6]
Register map - read/write properties A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 Read mode receive holding register (RHR) interrupt enable register (IER) interrupt identification register (IIR) line control register (LCR) modem control register (MCR)[1] line status register (LSR) modem status register (MSR) scratchpad register (SPR) divisor latch LSB (DLL)[2], [3] divisor latch MSB (DLH)[2], [3] enhanced feature register (EFR)[2], [4] Xon1 word[2], [4] Xon2 word[2], [4] Xoff1 word[2], [4] Xoff2 word[2], [4] trigger level register (TLR)[2], [5] FIFO ready register[2], [6] scratchpad register divisor latch LSB[2], [3] divisor latch MSB[2], [3] enhanced feature register[2], [4] Xon1 word[2], [4] Xon2 word[2], [4] Xoff1 word[2], [4] Xoff2 word[2], [4] trigger level register[2], [5] Write mode transmit holding register (THR) interrupt enable register FIFO control register (FCR) line control register modem control register[1]
A1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1
transmission control register (TCR)[2], [5] transmission control register[2], [5]
MCR[7] can only be modified when EFR[4] is set. Accessed by a combination of address pins and register bits. Accessible only when LCR[7] is logic 1. Accessible only when LCR is set to 10111111 (8hBF). Accessible only when EFR[4] = 1 and MCR[6] = 1, i.e., EFR[4] and MCR[6] are read/write enables. Accessible only when CSA or CSB = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).
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Table 10 lists and describes the SC16C752 internal registers.
Table 10: SC16C752 internal registers Shaded bits are only accessible when EFR[4] is set. A2 A1 A0 Register Bit 7 General Register Set[1] 0 0 0 0 0 0 0 0 1 RHR THR IER bit 7 bit 7 0/CTS interrupt enable[2] RX trigger level (MSB) FCR[0] bit 6 bit 6 0/RTS interrupt enable[2] bit 5 bit 5 0/Xoff[2] bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 Rx data available interrupt FIFO enable R W R/W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/ Write
0/X sleep modem receive THR mode[2] status line status empty interrupt interrupt interrupt 0/TX trigger level (LSB)[2] 0/Xoff DMA mode select TX FIFO reset RX FIFO reset
0
1
0
FCR
RX trigger 0/TX level (LSB) trigger level (MSB)[2] FCR[0] 0/CTS, RTS
W
0
1
0
IIR
interrupt interrupt priority priority bit 2 bit 1 parity enable
interrupt priority bit 0
interrupt status word length bit 0 DTR
R
0
1
1
LCR
DLAB
break control bit TCR and TLR enable
set parity parity type select 0/Xon Any THR empty DSR bit 5 bit 5 bit 5
number of word stop bits length bit 1 FIFO ready enable parity error RI bit 2 bit 2 bit 2 0 RTS
R/W
1
0
0
MCR
1x or 1x/4 clock
0/enable IRQ loop-back enable OP break interrupt CTS bit 4 bit 4 bit 4 framing error CD bit 3 bit 3 bit 3 0
R/W
1
0
1
LSR
0/error in THR and RX FIFO TSR empty CD bit 7 bit 7 bit 7 0 RI bit 6 bit 6 bit 6 0
overrun error DSR bit 1 bit 1 bit 1
data in receiver CTS bit 0 bit 0 bit 0
R
1 1 1 1 1
1 1 1 1 1
0 1 0 1 1
MSR SPR TCR TLR FIFO Rdy DLL DLH EFR
R R/W R/W R/W R
RX FIFO RX FIFO B status A status bit 5 bit 13 bit 4 bit 12
TX FIFO B TX FIFO status A status bit 1 bit 9 software flow control bit 1 bit 1 bit 1 bit 1 bit 1 bit 0 bit 8 software flow control bit 0 bit 0 bit 0 bit 0 bit 0
Special Register Set[3] 0 0 0 0 0 1 0 1 0 bit 7 bit 15 Auto CTS bit 6 bit 14 Auto RTS bit 3 bit 11 bit 2 bit 10 R/W R/W R/W
Enhanced Register Set[4] Special Enable software software character enhanced flow flow detect functions control control [2] bit 3 bit 2 bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 bit 3 bit 3 bit 3 bit 3 bit 2 bit 2 bit 2 bit 2
1 1 1 1
[1] [2]
0 0 1 1
0 1 0 1
Xon1 Xon2 Xoff1 Xoff2
bit 7 bit 7 bit 7 bit 7
bit 6 bit 6 bit 6 bit 6
R/W R/W R/W R/W
These registers are accessible only when LCR[7] = 0. The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
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[3] [4]
The Special Register set is accessible only when LCR[7] is set to a logic 1. Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to `BFHex'.
Remark: Refer to the notes under Table 9 for more register access information.
7.1 Receiver holding register (RHR)
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location zero of the FIFO is used to store the characters. Remark: In this case, characters are overwritten if overflow occurs. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character.
7.2 Transmit holding register (THR)
The transmitter section consists of the transmit holding register (THR) and the transmit shift register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs.
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7.3 FIFO control register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11 shows FIFO control register bit settings.
Table 11: Bit 7-6 FIFO Control Register bits description Description RCVR trigger. Sets the trigger level for the RX FIFO. 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters 5-4 FCR[5] (MSB), FCR[4] (LSB) TX trigger. Sets the trigger level for the TX FIFO. 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces FCR[5-4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function. 3 FCR[3] DMA mode select. Logic 0 = Set DMA mode `0' Logic 1 = Set DMA mode `1' 2 FCR[2] Reset TX FIFO. Logic 0 = No FIFO transmit reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] Reset RX FIFO. Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO.
Symbol FCR[7] (MSB), FCR[6] (LSB)
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7.4 Line control register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the line control register bit settings.
Table 12: Bit 7 Line Control Register bits description Description Divisor latch enable. Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch enabled. 6 LCR[6] Break control bit. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. Logic 0 = no TX break condition (normal default condition). Logic 1 = forces the transmitter output (TX) to a logic 0 to alert the communication terminal to a line break condition. 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1). Logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 LCR[4] Parity type select. Logic 0 = ODD Parity is generated (if LCR[3] = 1). Logic 1 = EVEN Parity is generated (if LCR[3] = 1). 3 LCR[3] Parity enable. Logic 0 = no parity (normal default condition). Logic 1 = a parity bit is generated during transmission and the receiver checks for received parity. 2 LCR[2] Number of Stop bits. Specifies the number of stop bits. 0 - 1 stop bit (word length = 5, 6, 7, 8) 1 - 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1-0 LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received. 00 - 5 bits 01 - 6 bits 10 - 7 bits 11 - 8 bits
Symbol LCR[7]
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7.5 Line status register (LSR)
Table 13 shows the line status register bit settings.
Table 13: Bit 7 Line Status Register bits description Description FIFO data error. Logic 0 = No error (normal default condition). Logic 1 = At least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. Logic 0 = Transmitter hold and shift registers are not empty. Logic 1 = Transmitter hold and shift registers are empty. 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. Logic 0 = Transmit hold register is not empty. Logic 1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled. 4 LSR[4] Break interrupt. Logic 0 = No break condition (normal default condition). Logic 1 = A break condition occurred and associated byte is 00, i.e., RX was LOW for one character time frame. 3 LSR[3] Framing error. Logic 0 = No framing error in data being read from RX FIFO (normal default condition). Logic 1 = Framing error occurred in data being read from RX FIFO, i.e., received data did not have a valid stop bit. 2 LSR[2] Parity error. Logic 0 = No parity error (normal default condition). Logic 1 = Parity error in data being read from RX FIFO. 1 LSR[1] Overrun error. Logic 0 = No overrun error (normal default condition). Logic 1 = Overrun error has occurred. 0 LSR[0] Data in receiver. Logic 0 = No data in receive FIFO (normal default condition). Logic 1 = At least one character in the RX FIFO.
Symbol LSR[7]
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is output directly onto the output data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO read pointer is incremented by reading the RHR.
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Remark: The three error bits (parity, framing, break) may not be updated correctly in the first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz. However, the second read is always correct. It is strongly recommended that when using this device with a clock faster than 36 MHz, that the LSR be read twice and only the second read be used for decision making. All other bits in the LSR are correct on all reads.
7.6 Modem control register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 14 shows modem control register bit settings.
Table 14: Bit 7 Modem Control Register bits description Symbol MCR[7]
[1]
Description Clock select. Logic 0 = Divide-by-1 clock input. Logic 1 = Divide-by-4 clock input.
6
MCR[6]
[1]
TCR and TLR enable. Logic 0 = no action. Logic 1 = Enable access to the TCR and TLR registers.
5
MCR[5]
[1]
Xon Any. Logic 0 = Disable Xon Any function. Logic 1 = Enable Xon Any function.
4
MCR[4]
Enable loop-back. Logic 0 = Normal operating mode. Logic 1 = Enable local loop-back mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4] and the TX output is looped back to the RX input internally.
3
MCR[3]
IRQ enable OP. Logic 0 = Forces INTA-INTB outputs to the 3-State mode and OP output to HIGH state. Logic 1 = Forces the INTA-INTB outputs to the active state and OP output to LOW state. In loop-back mode, controls MSR[7].
2
MCR[2]
FIFO Ready enable. Logic 0 = Disable the FIFO Rdy register. Logic 1 = Enable the FIFO Rdy register. In loop-back mode, controls MSR[6].
1
MCR[1]
RTS Logic 0 = Force RTS output to inactive (HIGH). Logic 1 = Force RTS output to active (LOW). In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled by hardware flow control.
0
MCR[0]
DTR Logic 0 = Force DTR output to inactive (HIGH). Logic 1 = Force DTR output to active (LOW). In loop-back mode, controls MSR[5].
[1]
MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.
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7.7 Modem status register (MSR)
This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 15 shows modem status register bit settings per channel.
Table 15: Bit 7 Modem Status Register bits description Description CD (Active-HIGH, logical 1). This bit is the complement of the CD input during normal mode. During internal loop-back mode, it is equivalent to MCR[3]. RI (Active-HIGH, logical 1). This bit is the complement of the RI input during normal mode. During internal loop-back mode, it is equivalent to MCR[2]. DSR (Active-HIGH, logical 1). This bit is the complement of the DSR input during normal mode. During internal loop-back mode, it is equivalent MCR[0]. CTS (Active-HIGH, logical 1). This bit is the complement of the CTS input during normal mode. During internal loop-back mode, it is equivalent to MCR[1]. CD. Indicates that CD input (or MCR[3] in loop-back mode) has changed state. Cleared on a read. RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed state from LOW to HIGH. Cleared on a read. DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has changed state. Cleared on a read. CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has changed state. Cleared on a read.
Symbol MSR[7]
6
MSR[6]
5
MSR[5]
4
MSR[4]
3 2 1 0
[1]
MSR[3] MSR[2] MSR[1] MSR[0]
The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR and MCR (in loop-back) registers are Active-HIGH.
7.8 Interrupt enable register (IER)
The interrupt enable register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW to HIGH. The INT output signal is activated in response to interrupt generation. Table 16 shows interrupt enable register bit settings.
Table 16: Bit 7 Interrupt Enable Register bits description Description CTS interrupt enable. Logic 0 = Disable the CTS interrupt (normal default condition). Logic 1 = Enable the CTS interrupt. 6 IER[6]
[1] [1]
Symbol IER[7]
RTS interrupt enable. Logic 0 = Disable the RTS interrupt (normal default condition). Logic 1 = Enable the RTS interrupt.
5
IER[5]
[1]
Xoff interrupt. Logic 0 = Disable the Xoff interrupt (normal default condition). Logic 1 = Enable the Xoff interrupt.
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Interrupt Enable Register bits description...continued Description Sleep mode. Logic 0 = Disable sleep mode (normal default condition). Logic 1 = Enable sleep mode. See Section 6.7 "Sleep mode" for details.
[1]
Table 16: Bit 4
Symbol IER[4]
3
IER[3]
Modem Status Interrupt. Logic 0 = Disable the modem status register interrupt (normal default condition). Logic 1 = Enable the modem status register interrupt.
2
IER[2]
Receive Line Status interrupt. Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt. Logic 0 = Disable the THR interrupt (normal default condition). Logic 1 = Enable the THR interrupt.
0
IER[0]
Receive Holding Register interrupt. Logic 0 = Disable the RHR interrupt (normal default condition). Logic 1 = Enable the RHR interrupt.
[1]
IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold.
7.9 Interrupt identification register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 17 shows interrupt identification register bit settings.
Table 17: Bit 7-6 5 4 3-1 0 Interrupt Identification Register bits description Description Mirror the contents of FCR[0]. RTS/CTS LOW-to-HIGH change of state. 1 = Xoff/Special character has been detected. 3-bit encoded interrupt. See Table 18. Interrupt status. Logic 0 = An interrupt is pending. Logic 1 = No interrupt is pending.
Symbol IIR[7:6] IIR[5] IIR[4] IIR[3:1] IIR[0]
The interrupt priority list is shown in Table 18.
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Interrupt priority list IIR[5] 0 0 0 0 0 0 1 IIR[4] 0 0 0 0 0 1 0 IIR[3] 0 1 0 0 0 0 0 IIR[2] 1 1 1 0 0 0 0 IIR[1] 1 0 0 1 0 0 0 IIR[0] 0 0 0 0 0 0 0 Source of the interrupt Receiver Line Status error Receiver time-out interrupt RHR interrupt THR interrupt Modem interrupt Received Xoff signal/ special character CTS, RTS change of state from active (LOW) to inactive (HIGH)
Table 18: Priority level 1 2 2 3 4 5 6
7.10 Enhanced feature register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows the enhanced feature register bit settings.
Table 19: Bit 7 Enhanced Feature Register bits description Description CTS flow control enable. Logic 0 = CTS flow control is disabled (normal default condition). Logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTS pin. 6 EFR[6] RTS flow control enable. Logic 0 = RTS flow control is disabled (normal default condition). Logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached. 5 EFR[5] Special character detect. Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. Received data is compared with Xoff-2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special character has been detected. 4 EFR[4] Enhanced functions enable bit. Logic 0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]. Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write enable. 3-0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 "Software flow control options (EFR[0:3])" on page 9.
Symbol EFR[7]
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7.11 Divisor latches (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Note that DLL and DLH can only be written to before sleep mode is enabled, i.e., before IER[4] is set.
7.12 Transmission control register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 20 shows transmission control register bit settings.
Table 20: Bit 7-4 3-0 Transmission Control Register bits description Description RX FIFO trigger level to resume transmission (0-60). RX FIFO trigger level to halt transmission (0-60).
Symbol TCR[7:4] TCR[3:0]
TCR trigger levels are available from 0-60 bytes with a granularity of four. Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that TCR[3:0] > TCR{7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious operation of the device.
7.13 Trigger level register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed with a granularity of 4. Table 21 shows trigger level register bit settings.
Table 21: Bit 7-4 3-0 Trigger Level Register bits description Description RX FIFO trigger levels (4-60), number of characters available. TX FIFO trigger levels (4-60), number of spaces available.
Symbol TLR[7:4] TLR[3:0]
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60 bytes are available with a granularity of four. The TLR should be programmed for N4, where N is the desired trigger level. When the trigger level setting in TLR is zero, the SC16C752 uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger level setting. When TLR is used for RX trigger level control, ICR[7:6] should be left at the default state, i.e., `00'.
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7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels.
Table 22: Bit 7-6 5 4 3-2 1 0 FIFO Ready Register bits description Description Unused; always 0. RX FIFO B status. Related to DMA. RX FIFO A status. Related to DMA. Unused; always 0. TX FIFO B status. Related to DMA. TX FIFO A status. Related to DMA.
Symbol FIFO Rdy[7:6] FIFO Rdy[5] FIFO Rdy[4] FIFO Rdy[3:2] FIFO Rdy[1] FIFO Rdy[0]
The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back is disabled. The address is 111.
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8. Programmer's guide
The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access. Some streamlining through interleaving can be obtained when programming all the registers.
Table 23: Command Set baud rate to VALUE1, VALUE2 Register programming guide Actions Read LCR (03), save in temp Set LCR (03) to 80 Set DLL (00) to VALUE1 SET DLM (01) to VALUE2 Set LCR (03) to temp Set Xoff-1, Xon-1 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff-1 (06) to VALUE1 SET Xon-1 (04) to VALUE2 Set LCR (03) to temp Set Xoff-2, Xon-2 to VALUE1, VALUE2 Read LCR (03), save in temp Set LCR (03) to BF Set Xoff-2 (07) to VALUE1 SET Xon-2 (05) to VALUE2 Set LCR (03) to temp Set software flow control mode to VALUE Read LCR (03), save in temp Set LCR (03) to BF Set EFR (02) to VALUE Set LCR (03) to temp Set flow control threshold to VALUE Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to 40 + temp3 Set TCR (06) to VALUE Set MCR (04) to temp3 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1
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Register programming guide...continued Actions Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to 40 + temp3 Set TLR (07) to VALUE Set MCR (04) to temp3 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1
Table 23: Command
Set TX FIFO and RX FIFO thresholds to VALUE
Read FIFO Rdy register
Read MCR (04), save in temp1 Set temp2 = temp1 x EF [1] Set MCR (04) = 40 + temp2 Read FFR (07), save in temp2 Pass temp2 back to host Set MCR (04) to temp1
Set prescaler value to divide-by-1
Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to temp3 x 7F [1] Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1
Set prescaler value to divide-by-4
Read LCR (03), save in temp1 Set LCR (03) to BF Read EFR (02), save in temp2 Set EFR (02) to 10 + temp2 Set LCR (03) to 00 Read MCR (04), save in temp3 Set MCR (04) to temp3 + 80 Set LCR (03) to BF Set EFR (02) to temp2 Set LCR (03) to temp1
[1]
x sign here means bit-AND.
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9. Limiting values
Table 24: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO Tamb Tstg
[1]
Parameter supply voltage input voltage output voltage operating ambient temperature storage temperature
Conditions
Min -0.3 -0.3
Max 7 VCC + 0.3 VCC + 0.3 +85 +150
Unit V V V C C
in free-air
-40 -65
Stresses beyond those listed under Limiting values may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
10. Static characteristics
Table 25: DC electrical characteristics VCC = 2.5 V, 3.3 V 10% or 5 V 10%. Symbol Parameter VCC VI VIH VIL VO VOH supply voltage input voltage HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output voltage IOH = -8 mA IOH = -4 mA IOH = -800 A IOH = -400 A VOL LOW-level output voltage[7] IOL = 8 mA IOL = 4 mA IOL = 2 mA IOL = 1.6 mA Ci Tamb Tj input capacitance operating ambient temperature junction temperature clock speed clock duty cycle ICC
[1] [2]
[3] [1]
Conditions Min 0 1.6 0 1.85 1.85 -40 0 f = 5 MHz
[6]
2.5 V Nom 25 25 50 Max VCC VCC 0.65 VCC 0.4 0.4 18 85 125 50 3.5 Min 0 2.0 0 2.0 2.0 -40 0 VCC - 10% VCC
3.3 V and 5 V Nom 25 25 50 Max VCC + 10% VCC - 10% VCC
Unit
VCC + 10% V VCC VCC 0.8 VCC 0.4 0.4 18 85 125 80 4.5 V V V V V V V V V V V V pF C C MHz % mA
[1]
[2] [4] [5] [4] [5] [4] [5] [4] [5]
[8]
supply current
-
Meets TTL levels, VIO(min) = 2 V and VIH(max) = 0.8 V on non-hysteresis inputs. Applies for external output buffers.
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Dual UART with 64-byte FIFO
[3] [4] [5] [6]
[7] [8]
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 C. The customer is responsible for verifying junction temperature. These parameters apply for D7-D0. These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. Measurement condition, normal operation other than sleep mode: VCC = 3.3 V; Tamb = 25 C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of 1. Except x2, VOL = 1 V typical. Applies to external clock; crystal oscillator max. 24 MHz.
11. Dynamic characteristics
Table 26: AC electrical characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V 10% or 5 V 10%, unless specified otherwise. Symbol td1 td2 td3 td4 td5 td6 td7 td8 td9 td10 td11 td12 td13 td14 td15 td16 td17 td18 td19 th1 th2 th3 th4 th5 Parameter IOR delay from chip select read cycle delay delay from IOR to data data disable time IOW delay from chip select write cycle delay delay from IOW to output delay to set interrupt from modem input delay to reset interrupt from IOR delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY delay from start to reset TXRDY delay between successive assertion of IOW and IOR chip select hold time from IOR chip select hold time from IOW data hold time address hold time hold time from XTAL1 clock HIGH-to-LOW transition to IOW or IOR release 25 pF load 25 pF load 25 pF load 25 pF load
[1]
Conditions Min 10 25 pF load 25 pF load 25 pF load 20 10 25 8 0 0 15 0 20
2.5 V Max 77 15 100 100 100 1 100 100 24 100 1 100 100 16 20 0
3.3 V and 5 V Min 20 10 25 8 0 0 15 0 20 Max 26 15 33 24 24 1 29 100 24 70 1 75 70 16 20 -
Unit ns ns ns ns ns ns ns ns ns Rclk baud rate ns ns Rclk baud rate ns Rclk baud rate ns ns Rclk baud rate ns ns ns ns ns ns
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Table 26: AC electrical characteristics...continued Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V 10% or 5 V 10%, unless specified otherwise. Symbol tp1, tp2 tp3 t(RESET) tsu1 tsu2 tsu3 tw1 tw2
[1] [2]
Parameter clock cycle period clock speed RESET pulse width address set-up time data set-up time set-up time from IOW or IOR assertion to XTAL1 clock LOW-to-HIGH transition IOR strobe width IOW strobe width
Conditions Min 10
[3]
2.5 V Max 48 6 -
3.3 V and 5 V Min Max 80 -
Unit ns MHz ns ns ns ns ns ns
200 0 16 20 77
200 0 16 20 30 30
[2]
30
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1 clock cycle.
1 IOWstrobe max = ------------------------------------2 ( Baudrate max )
= 333 ns (for Baudratemax = 1.5 Mbits/s) = 1 s (for Baudratemax = 460.8 kbits/s) = 4 s (for Baudratemax = 115.2 kbits/s)
[3]
Applies to external clock; crystal oscillator max 24 MHz.
11.1 Timing diagrams
A0-A2
VALID ADDRESS tsu1 th4
CSA, CSB td1
ACTIVE th1 tw1 td2
IOR
ACTIVE td4
td3
D0-D7
DATA
002aaa235
Fig 13. General read timing.
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A0-A2
VALID ADDRESS tsu1 th4
CSA, CSB td5
ACTIVE th2 tw2 td6
IOW
ACTIVE
tsu2
th3
D0-D7
DATA
002aaa236
Fig 14. General write timing.
td19
IOW IOR tsu3 th5
XTAL1
002aaa237
Fig 15. Alternate read/write strobe timing.
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Dual UART with 64-byte FIFO
IOW
ACTIVE
td7
RTSA, RTSB DTRA, DTRB
CHANGE OF STATE
CHANGE OF STATE
CDA, CDB CTSA, CTSB DSRA, DSRB td8
CHANGE OF STATE
CHANGE OF STATE
td8
INTA, INTB
ACTIVE
ACTIVE
ACTIVE
td9
IOR
ACTIVE
ACTIVE
ACTIVE
td8
RIA, RIB
CHANGE OF STATE
002aaa238
Fig 16. Modem input/output timing.
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Dual UART with 64-byte FIFO
START BIT DATA BITS (5-8)
PARITY BIT
STOP BIT
NEXT DATA START BIT
RXA, RXB
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS td10 7 DATA BITS INTA, INTB ACTIVE
td11
IOR
ACTIVE
16 BAUD RATE CLOCK
002aaa239
Fig 17. Receive timing.
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Dual UART with 64-byte FIFO
START BIT DATA BITS (5-8)
PARITY BIT
STOP BIT
NEXT DATA START BIT
RXA RXB
D0
D1
D2
D3
D4
D5
D6
D7
td15 ACTIVE DATA READY td16
RXRDYA RXRDYB
IOR
ACTIVE
002aaa240
Fig 18. Receive ready timing in non-FIFO mode.
START BIT DATA BITS (5-8)
PARITY BIT
STOP BIT
RXA RXB
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT REACHES THE TRIGGER LEVEL
td15 ACTIVE DATA READY td16
RXRDYA RXRDYB
IOR
ACTIVE
002aaa241
Fig 19. Receive ready timing in FIFO mode.
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Dual UART with 64-byte FIFO
START BIT DATA BITS (5-8) TXA, TXB
PARITY BIT
STOP BIT
NEXT DATA START BIT
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS td12 INTA, INTB td13 ACTIVE TX READY
td14
IOW
ACTIVE
ACTIVE
16 BAUD RATE CLOCK
002aaa242
Fig 20. Transmit timing.
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Dual UART with 64-byte FIFO
START BIT DATA BITS (5-8)
PARITY BIT
STOP BIT
NEXT DATA START BIT
TXA, TXB
D0
D1
D2
D3
D4
D5
D6
D7
IOW
ACTIVE
D0-D7
BYTE #1
td18
td17 TXRDYA, TXRDYB ACTIVE TRANSMITTER READY
TRANSMITTER NOT READY
002aaa243
Fig 21. Transmit ready timing in non-FIFO mode.
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Dual UART with 64-byte FIFO
START BIT DATA BITS (5-8)
PARITY BIT
STOP BIT
TXA, TXB
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
IOW
ACTIVE
td18
D0-D7
BYTE #32
td17
TXRDYA, TXRDYB
TRIGGER LEAD
002aaa244
Fig 22. Transmit ready timing in FIFO mode.
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Dual UART with 64-byte FIFO
12. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 23. LQFP48 package outline (SOT313-2).
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13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 220 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
13.5 Package related soldering information
Table 27: Package[1] BGA, LBGA, LFBGA, SQFP, SSOP-T[3], TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[4] Reflow[2] suitable suitable
suitable not recommended[5][6] not recommended[7]
suitable suitable suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
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These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[3]
[4]
[5] [6] [7]
14. Revision history
Table 28: Rev Date 04 20030620 Revision history CPCN Description Product data (9397 750 11635); ECN 853-2379 30031 of 16 June 2003. Modifications:
*
03 02 01 20030313 20021216 20020910 -
Figure 12 "Crystal oscillator connections." on page 18: capacitors' values changed and added connection with resistor.
Product data (9397 750 11196); ECN 853-2379 29623 of 10 March 2003. Product data (9397 750 10811); ECN 853-2379 29261 of 06 December 2002. Product data (9397 750 09575); ECN 853-2379 28891 of 10 September 2002.
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15. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 11635
Fax: +31 40 27 24825
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Dual UART with 64-byte FIFO
Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Software flow control . . . . . . . . . . . . . . . . . . . . 9 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software flow control example . . . . . . . . . . . . 10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt mode operation . . . . . . . . . . . . . . . . 13 Polled mode operation . . . . . . . . . . . . . . . . . . 13 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 14 Single DMA transfers (DMA mode 0/FIFO disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block DMA transfers (DMA mode 1). . . . . . . . 15 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Break and time-out conditions . . . . . . . . . . . . 16 Programmable baud rate generator . . . . . . . . 16 Register descriptions . . . . . . . . . . . . . . . . . . . 18 Receiver holding register (RHR). . . . . . . . . . . 20 Transmit holding register (THR) . . . . . . . . . . . 20 FIFO control register (FCR) . . . . . . . . . . . . . . 21 Line control register (LCR) . . . . . . . . . . . . . . . 22 Line status register (LSR) . . . . . . . . . . . . . . . . 23 Modem control register (MCR) . . . . . . . . . . . . 24 Modem status register (MSR). . . . . . . . . . . . . 25 Interrupt enable register (IER) . . . . . . . . . . . . 25 Interrupt identification register (IIR) . . . . . . . . 26 Enhanced feature register (EFR) . . . . . . . . . . 27 Divisor latches (DLL, DLH) . . . . . . . . . . . . . . . 28 Transmission control register (TCR) . . . . . . . . 28 Trigger level register (TLR) . . . . . . . . . . . . . . . 28 FIFO ready register. . . . . . . . . . . . . . . . . . . . . 29 Programmer's guide . . . . . . . . . . . . . . . . . . . . 30 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 34 42 43 43 43 43 44 44 45 46 46 46
(c) Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 20 June 2003 Document order number: 9397 750 11635

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